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? Scatter-gather (using the primary descriptor to configure the alternate descriptor)
? Each channel has a programmable transfer length
? A DMA channel can be triggered by any of several sources:
? Communication modules (USART, UART, LEUART)
? Timers (TIMER)
? Analog modules (DAC, ADC)
? Software
? Programmable mapping between channel number and peripherals - any DMA channel can be
triggered by any of the available sources
? Interrupts upon transfer completion
? Data transfer to/from LEUART in EM2 is supported by the DMA, providing extremely low energy
consumption while performing UART communications
8.3 Block Diagram
An overview of the DMA and the modules it interacts with is shown in Figure 8.1 (p. 39) .
Figure 8.1. DMA Block Diagram
Interrupts
Cortex-M3
AHB
APB block
AHB block
AHB to
APB
bridge
Configuration
control
APB
m em ory
m apped
registers
AHB-Lite
m aster
interface
DMA data
transfer
Configuration
Erro r
Peripheral
Channel
select
REQ/
DMA Core
Channel
ACK
done
Peripheral
DMA control block
The DMA Controller consists of four main parts:
? An APB block allowing software to configure the DMA controller
? An AHB block allowing the DMA to read and write the DMA descriptors and the source and destination
data for the DMA transfers
? A DMA control block controlling the operation of the DMA, including request/acknowledge signals for
the connected peripherals
? A channel select block routing the right peripheral request to each DMA channel
8.4 Functional Description
The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory
without involvement from the processor core. This can be used to increase system performance by
2011-04-12 - d0001_Rev1.10
39
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